Hello, I have a Altera Cyclone III Development Board and try to synchronize some Videostreams. They are delayed horizontal and vertical. Is it possible to synchronize them onboard without using external elements? GenLock seems not to work, because I don't have a VCXO onboard. Thank you

You can synchronize all four video streams, you need a frame buffer for each input. This can be done internally in the FPGA if there is enough embedded memory to buffer a frame of video for each stream. If you need to genlock the output, you'll need external devices to generate your output timing.

--- Quote Start --- You can synchronize all four video streams, you need a frame buffer for each input. --- Quote End --- Hello mess, I have following configuration several times in parallel: CVI - Clipper - FrameBuffer - Scaler - CVO I think the delay between the videostreams has his source at the clippers. How do you think I can synchronize the FrameBuffer? Thank you

It probably isn't the clipper, as it's a simple block with fixed delays through it. Are your four video inputs to the FPGA synchronized to each other? If not, then the delays are at your source. The frame buffer should have horizontal and vertical control pulses for the input and output paths. The input H&V pulses should come from each input, and the output H&V pulses should be the same for all four outputs.

--- Quote Start --- Are your four video inputs to the FPGA synchronized to each other? --- Quote End --- The inputs are the same at each CVI, I splitted the source signal out of the SOPC Builder. Input => SOPC System => Self Programmed Mixer => Output SOPC System: CVI - Clipper - FrameBuffer - Scaler - CVO CVI - Clipper - FrameBuffer - Scaler - CVO CVI - Clipper - FrameBuffer - Scaler - CVO I clipped different parts of the video and have scaled them up. If I clipp always the same parts of a videostream, I get only an offset of a few pixels, which I can compensate by a self written Verilog code. But when I clipp different parts, i get an offset of around ~50% of all lines

Can you explain exactly what it is that you are trying to achieve? What are the four video inputs? Four cameras? Something else? Are you gen-locking the cameras with a sync pulse out from the FPGA? If you are using cameras and went them to be synchronized then the FPGA needs to be the timing master and you need it to send out a gen-lock sync pulse to each camera, so that they all start exposing simultaneously and will also all be read out at the exact same rate (Frames per Second). Maybe you can upload some screen shots of the offsets you are talking about. --- Quote Start --- The inputs are the same at each CVI, I splitted the source signal out of the SOPC Builder. Input => SOPC System => Self Programmed Mixer => Output SOPC System: CVI - Clipper - FrameBuffer - Scaler - CVO CVI - Clipper - FrameBuffer - Scaler - CVO CVI - Clipper - FrameBuffer - Scaler - CVO I clipped different parts of the video and have scaled them up. If I clipp always the same parts of a videostream, I get only an offset of a few pixels, which I can compensate by a self written Verilog code. But when I clipp different parts, i get an offset of around ~50% of all lines --- Quote End ---

Videostrem synchronisation | Altera Community

12 Replies

Altera_Forum
Honored Contributor
13 years ago
I'm not familiar with Altera's VIP, so I can't comment on specifics.

However, since you are taking one input video source and slicing it up into 9 images, you should have a common clock and you don't need to worry about genlock.

In order to align all of your images to keep you mixer happy, you will have to delay the readout of each frame buffer to the one that will be the last to arrive. In your case, the clipper for the lower right image.
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---

In order to align all of your images to keep you mixer happy, you will have to delay the readout of each frame buffer to the one that will be the last to arrive. In your case, the clipper for the lower right image.
--- Quote End ---

Hi mess,
until yesterday, I thought that my pictures are delayed only horizontal and so I delayed all other streams till they are on the position of the last one.
But I have done this with onchip FIFOs.
And now, when I see that I have a vertical delay, my onchip memory for the FIFOs is much to small to do this job. =(

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Videostrem synchronisation

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