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Altera_Forum
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14 years ago

Video Scaler in VIP

Hi, I try to implement a hardware design which scales an incoming video signal. With the new resolution the signal should output on a display. My Plan is to do this with the help of the “Video and...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I noticed that about every third or fourth time I programmed the FPGA the systems works. It seems to be a issue with the sync.

In the settings of the CVO there is a input field "Fifo level at which to start output"

Can you advise a value for this field?

(The Resolution of the screen is 1366x768)