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New Contributor

6 years ago

vid_de signal behavior in HDMI Intel FPGA IP sink (RX)

Hi, I wander if the vid_de signals (there are 2 of them in Cyclone 10 implementation because the IP outputs 2 pixels at a time. My question is if the vid_de signals, which are Video Data Enable, be...

Deshi_Intel

Regular Contributor

6 years ago

Hi,

Sorry, I am not aware you are referring to HDMI sink.

I am not familiar with pixel valid signal.

If you look at the next page of HDMI user guide doc (page 102)

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_hdmi.pdf
HDMI IP sink does have locked signal (to detect TMDS color) and vid_lock signal (to detect problematic frame)

Are you looking for something like these status signal ?

Thanks.

Regards,

dlim

Forum Discussion

vid_de signal behavior in HDMI Intel FPGA IP sink (RX)

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