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EHait
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6 years ago

vid_de signal behavior in HDMI Intel FPGA IP sink (RX)

Hi, I wander if the vid_de signals (there are 2 of them in Cyclone 10 implementation because the IP outputs 2 pixels at a time. My question is if the vid_de signals, which are Video Data Enable, be...
EHait's avatar
EHait
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6 years ago

hi, Dim., thanx.

In the SINK part of HDMI, (the video RX) the vid_de is output from the core .

So the question is if it works as "pixel valid" signal where it may also be invalid in some clock cycles during the "active video" region?