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EHait's avatar
EHait
Icon for New Contributor rankNew Contributor
6 years ago

vid_de signal behavior in HDMI Intel FPGA IP sink (RX)

Hi, I wander if the vid_de signals (there are 2 of them in Cyclone 10 implementation because the IP outputs 2 pixels at a time. My question is if the vid_de signals, which are Video Data Enable, be...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

vid_de is input port to Intel FPGA HDMI IP that indicate active picture region only.

This is input port controlled by user logic design and not output port from HDMI IP.

If HDMI IP see "1" on vid_de then HDMI will process the data as "active video".

Thanks.

Regards,

dlim