VHDL simulation of Uniphy DDR3 controller

Thank you for pointing me to this errata list.

According to this list, the root cause of my problem is that I should not use the half rate bridge feature (feature that allows to implement a local interface with half the rate of the clock sent to the memory device).

Unfortunately, the document states that:

- The half rate bridge feature is not supported by Quartus 10.1

- The half rate bridge feature is supported by Quartus 10.0, but attempts to generate a VHDL IP leads to verilog files.

This means that UniPHY is not a usable option for me yet.

I'll switch back to a good old ALTMEMPHY solution then ...