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Honored Contributor
Honored ContributorVHDL simulation of Uniphy DDR3 controller
Hello, I have no idea what I'm doing wrong. I'm generating a VHDL DDR3 Uniphy controller with the MegaWizard (Quartus 10.1). I wanted to simulate the example design, but I 'm running int...
Altera_ForumHonored Contributor
Honored ContributorThank you for pointing me to this errata list.
According to this list, the root cause of my problem is that I should not use the half rate bridge feature (feature that allows to implement a local interface with half the rate of the clock sent to the memory device). Unfortunately, the document states that: - The half rate bridge feature is not supported by Quartus 10.1 - The half rate bridge feature is supported by Quartus 10.0, but attempts to generate a VHDL IP leads to verilog files. This means that UniPHY is not a usable option for me yet. I'll switch back to a good old ALTMEMPHY solution then ...
