VHDL-Code with Avalon Bus Interface-/ and VHDL-Video-System-Interface-Ports

Thanks Kevin, this help me well.

But now I have another problem:

Here the complete vhdl-code:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

USE ieee.numeric_std.all;

ENTITY ime_avalon_xy_detector IS

PORT

(

-- Avalon Conduit to VHDL_Detector Clock Interface

coe_iVGA_CLK : in std_logic;

coe_iRST_N : in std_logic;

-- Avalon Conduit to VHDL_Detector IN-Ports

coe_iVGA_R : in std_logic_vector(9 downto 0);

coe_iVGA_VS : in std_logic;

-- Avalon Clock Interface

csi_clk : in std_logic;

csi_rst_n : in std_logic;

-- Avalon-MM Interface / Slave Port

avs_address : in std_logic;

avs_write : in std_logic;

avs_writedata : in std_logic_vector(31 downto 0);

avs_read : in std_logic;

avs_readdata : out std_logic_vector(31 downto 0)

);

END ENTITY ime_avalon_xy_detector;

--

ARCHITECTURE rtl OF ime_avalon_xy_detector IS

SIGNAL coordinate_wr : std_logic_vector(31 downto 0);

SIGNAL coordinate_rd : std_logic_vector(31 downto 0);

SIGNAL x : std_logic_vector(15 downto 0);

SIGNAL y : std_logic_vector(15 downto 0);

SIGNAL dat_0 : integer range 0 to 1000000 := 100000; -- 0x186A0

SIGNAL dat_1 : integer range 0 to 1000000 := 111111; -- 0x1B207

BEGIN

write_proc: process(csi_clk, csi_rst_n)

begin

if csi_rst_n = '0' then

coordinate_wr <= (others => '0');

x <= (others => '0');

y <= (others => '0');

elsif rising_edge(csi_clk) then

if avs_write = '1' then

coordinate_wr <= avs_writedata;

end if;

end if;

end process write_proc;

read_proc: process(csi_clk, csi_rst_n)

begin

if csi_rst_n = '0' then

coordinate_rd <= (others => '0');

avs_readdata <= (others => '0');

x <= (others => '0');

y <= (others => '0');

elsif rising_edge(csi_clk) then

coordinate_rd <= coordinate_wr;

if avs_address = '0'then

coordinate_rd <= std_logic_vector(to_unsigned(dat_1, 32));

elsif avs_address = '1' then

coordinate_rd <= std_logic_vector(to_unsigned(dat_0, 32));

end if;

if avs_read = '1' then

avs_readdata <= coordinate_rd;

end if;

end if;

end process read_proc;

END ARCHITECTURE rtl;

in this case the NiosII can not load the prgram in ram. Here the messagge:

Verifying 00080000 ( 0%)

Verify failed between address 0x80000 and 0x8D0DB

Leaving target processor paused

but when I change the part with the avs_address as below:

if avs_address = '0'then

coordinate_rd <= std_logic_vector(to_unsigned(dat_0, 32));

elsif avs_address = '1' then

coordinate_rd <= std_logic_vector(to_unsigned(dat_1, 32));

end if;

the NiosII will work good.

Thats very strange.....

Have you any idea???????