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Altera_Forum
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14 years ago

Verilog basics - isolating a bit in a sum

Inside an always statement: c <= a + b; s <= c[7]; What if I wanted to do: s <= (a+b)[7]; It does not work as such (compiler error), but it'd be convenient in that I do not want t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

You can simply define s as a wire and use an assign statement