Altera_Forum
Honored Contributor
Honored ContributorUsing UniPHY leaving RUP and RDN unconnected for a DDR2 SDRAM controller
is there a way to implement a UniPHY DDR2 SDRAM controller leaving RUP and RDN pins unconnected i.e. without OCT?
Forum Discussion
Altera_ForumHonored Contributor
Honored ContributorResults from stripping out all mention of "50 Ohm" in my constraints:
Same failure as Antti - Error: Output buffer atom "mts_core_nios:mts_core_nios_1|uniphy_qdrii_0:the_uniphy_qdrii_0|uniphy_qdrii_0_controller_phy:controller_phy_inst|uniphy_qdrii_0_memphy_top:memphy_top_inst|uniphy_qdrii_0_memphy:umemphy|uniphy_qdrii_0_io_pads:uio_pads|uniphy_qdrii_0_write_pads:uwrite_pads|uniphy_qdrii_0_write_d_iobuf:uwrite_d_iobuf|obufa_0" has port "SERIESTERMINATIONCONTROL[0]" connected, but does not use calibrated on-chip termination File: C:/firmware/projects/Proj_137_UC_S2_Extremecard_Stratix/trunk/mts_core_testing_q10/uniphy_qdrii_0_write_d_iobuf.v Line: 74
