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Altera_Forum
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11 years ago

Using Stratix V Transceiver native PHY core in the place of Arriai V PHY core

Hi All, Is it possible to directly replace the Transceiver native PHY core of Arria V GZ with Stratix V Transceiver native PHY core? If so how can it be implemented. Though its been stated Arria ...
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Altera_Forum
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11 years ago

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There are certain transceiver core IP output signals which cannot be utilized in 10 G mode like datakchar which I am using currently in standard PCS mode. These essential signals automatically disappear when I select 10G mode and standard PCS.

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Ok, that makes sense.

I'm not sure if you know this, but you can lie to Quartus :)

For example, lets say you nominally use a 125MHz reference and configure the IP for 125MHz x 64 = 8000Mbps lanes. If the 125MHz reference is programmable, eg., you have a synthesizer connected to the REFCLK input via an SMA connector, then you can program the synthesizer for 156.25MHz and the PHY will operate at 10Gbps just fine. How can you tell its working? You use the Transceiver Toolkit and check the eye pattern sweep in loopback mode. If you're not getting errors, then things appear to be working. To determine the range of frequencies over which this lie works, I'll run the transceiver toolkit loopback test, modify the synthesizer frequency slightly (+10MHz), clear bit-errors and then wait to see if there are bit errors at this new setting.

Cheers,

Dave