using modelsim simulation -> "Avalon® Verification IP Suite Design Example"

i tried another way ..

log -novopt -reportprogress 300 -work work ./slave_bfm_sopc.v

-> no exist "slave_bfm_sopc.v" files

log -novopt -reportprogress 300 -work work ./slave_bfm_sopc.sopc

-> modelsim cannot understand .sopc files

so i tried the pdf (Avalon Verification IP Suite, #187)

example Qsys design [avlmm_1x1_verilog.zip]

- Avalon_mm-BFM [M] <---> [S] Avalon_mm-BFM

- Simulation well working like that : Modelsim -> File -> Load -> Macro file... -> run_simulation.tcl

my goal is.. Verification what i designed Avalon mm Slave Logic [.. in progress]

[-----------------------------QSys--------------------------------] [-FPGA Logic for Avalon mm Verification-]

- Avalon_mm-BFM [M] <---> [S] Avalon_mm-Salve [Conduit] <---> Avalon_mm_Interface Logic