using JESD204B example design for Arria 10 (using RTL State Machine Control Unit version) with AD9250 ADC.

Hi Nathan,

Thank you for the info. It has help me make some progress but not quite there yet.

Now I am able to get lane0 to initialise but never lane 1. that is rx_pcs_data_valid0 goes high and I get the ‘K’ initialisation characters 0xBC. rx_pcs_data_valid1 never goes high so the core is unable to send the sync signal.

Any ideas why this may be so?

These are the commands I use to initialise the ADC.

# #AD9250 simple config to subclass 0,scrambling enabled

master_write_32 $m 0x4 0x005F15; #2, write 0x15 to link control 1 register 0x5F to disable the lane

master_write_32 $m 0x4 0x006E81; #2, write 0x81 to parameter SCR/L register 0x6E to enable scrambler

master_write_32 $m 0x4 0x00701F; #2, write 0x1F to parameter K register 0x70 for K=32

master_write_32 $m 0x4 0x005E22; #2, write 0x22 to quick config register 0x5E for L=2, M=2

master_write_32 $m 0x4 0x00730F; #2, address 0x73xx (0x2F to parameter for subclass 1(0x0F for subclass 0)

master_write_32 $m 0x4 0x00FF01; #2, write 0x01 to device update register 0xFF to update the settings

master_write_32 $m 0x4 0x005F14; #2, write 0x14 to link control 1 register 0x5F to enable the lane

Am I missing anything?

It seems like somehow I only enable lane 0.

any help will be deeply appreciated