using hard IP libraries in cadance simulator

Thanks Shyan for replying.

I can able to use hard IP libraries and also able to simulate in cadence.

Now the issue is I saw there is problem with pcie_ptile Avalon st Ip as If i simulate this IP, the simulation stucks in 0.0ns in cadence version use incisive 20.018 .

parameters are gen3x8, 256dp 250mhz.

I tried simulating the example design but there also it shows message as "pcie_ed_tb.dut_pcie_tb.dut_pcie_tb.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp.inst.dut.inst.inst.maib_and_tile.z1565a.ctp_tile_encrypted_inst.PROTECTED: The downstream component is backpressuring by deasserting ready, but the upstream component can't be backpressured."

and it stops, its not going further to run the test cases which are included in the example design bfm. example design can be simulate with vcs only.

for simulation i used vcs 2019 version. Ip was generated for stratix10 device 1SD280PT2F55E2VGS1 from quartus 19.4.