Honored Contributor
Honored ContributorHello,
Maxim wrote --- Quote Start --- The corresponding reference documentation is inadequate in terms of how the desired design can be implemented. --- Quote End --- I understand the complaints in so far, as the reference design doc (AN431) doesn't explicitely tell how to extent the provided PCIe-to-DDR2 design, e. g. how to share DDR2 instance with another module within your design. User surely would enjoy an instructive example of this kind, but I think, some work must be done by the developer himself. The basic point is to understand the interfaces available with PCIe and DDR2 controller core. They are well documented in AN431 and in the respective core user guides to my opinion, but probably require some effort to get complete command on it. I participated in an Arria GX design, one step in testing the hardware was porting the PCIe-to-DDR2 reference design. With Arria GX, a different DDR2 controller is used, but also the native interface in connecting PCIe to RAM. I was mainly engaged with hardware aspects, but I know, that the native interface is almost similar to Avalon and utilizes handshake signals. With their help, it should be possible to insert a multiplexer in the data path to connect your design part. Regards, Frank
