It looks like the code to generate was_valid causes it to assert but never negate so I added an else to the if that sets that bit. That caused an issue lining up the data_count value with the incoming data when ready is only asserted for a single clock cycle. (Which happens frequently to my module according to SignalTap.)
That got me wondering: why would the sink be asserting ready for only a single clock cycle? It negates it before it even gets a valid. My test system gets into a state where ready is asserted for a single clock every 8 clocks. I haven't been able to go back far enough to see how long it is in this state or what caused it. There's even a point in my source state machine where it pauses for a clock at the end of a data packet and the sink will assert ready for 1 clock, take it away with no valid at all, and then re-assert it 8 clocks later. Is that how it operates when the data pipe is starved or something? I don't ever see that behavior from TPG.