Using a different mem_ref_clk on an EMIF IP than the recommended

Hi Sir,

The EMIF IP is validated on our board with osc that direct supply EMIF IP PLL_REF_CLK pin. The connection that you did is similar to PLL cascading within the FPGA. And if you make the cascading,

the IP rules checker will give you a fitter error. However, your case, the tools unable to detect it because you supply the clock to a IOPLL of the FPGA, the you route the clock out from FPGA and back to the PLL_REF_CLK pin of the EMIF IP. But the connection scheme is similar with the PLL cascade within the FPGA and it is even worse because routing out the clock outside the FPGA will affected by external noise. This connection definitely will create more jitter and timing issue is expected. In conclusion, I would say the connection is invalid. And if you want to characterize further, you can measure the jitter of the clock that you route back to FPGA from pll output pin. Compare it with the clock from oscillator.

Hope this helps.

Thanks

Regards,

NAli1