Using a different mem_ref_clk on an EMIF IP than the recommended

Thanks for your replies,

1. We are aware that using the recommended frequency yields the best jitter performance and bandwidth. That's the frequency we will eventually use once we get our failing paths solved.

2. We are feeding a 150MHz clock into a PLL that expects 200MHz, so we are as well expecting a slower memory clock (600MHz). This will of course deprecate the performance of our design, but that's a downside we can work with at this point in the project if that gets us a user clock in which we can have some timing certainty (Quarter usr clock configuration: 600MHz/4 = 150MHz).

3. Yes, 150MHz is not on the selectable frequencies list for an 800MHz memory clock. If we configured the PLL frequency for 100MHz (which is the immediate lower value selectable after 200MHz), the memory clock would be 800MHz and the user clock 800MHz/4 = 200MHz, which defeats our purpose of having a slower user clock.

So far we have been able to test reference clock inputs as low as 100MHz (for a 200MHz configured EMIF) and ran memory tests for a couple of hours without issues. We wanted to know if any analog engineer with knowledge on the inner workings of the EMIF PLLs had any concern since there might be RC circuitry that could be affected by the significative difference in reference clock frequencies.

Thanks

Gsus