Using a different mem_ref_clk on an EMIF IP than the recommended

Hi GSuS,

I understand that in the EMIF IP you have set to 200MHz reference clock (listed in the IP), but actually the FPGA pin is getting 150MHz reference clock which is not listed in the list of possible reference frequencies.

In my view, It would not generate 800MHz memory clock with 150MHz. The reason being, when you select 200MHz as the input reference clock, the IP configures all the PLLs inside EMIF IP such that it assumes 200MHz input clock and does the required calculation of M & N (multiplication and division) values so that it will output 800MHz memory clock and 200MHz user clock (quarter/full rate controller). These values are static for one FPGA binary. When you feed 150MHz instead of 200MHz, the PLL blocks multiply and divide the reference clock with the previously set M & N values.

Simple example, we need to multiply by 4 to get 800MHz from 200MHz. Now if input frequency is 150MHz, then 150*4 = 600MHz. So, the design may work for some time with feeding the clock other than set clock in the EMIF IP, but it is not guaranteed to work continuously or provide the required performance/bandwidth.

With Regards,

HPB