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MamaSaru's avatar
MamaSaru
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2 months ago
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User controlled burst refresh

Hi, I have a problem regarding DDR3 EMIF IP can't bursting user control refresh. I am debugging my EMIF test design on Cyclone 10 GX development board. The situation is that it takes long time to ...
  • MamaSaru's avatar
    1 month ago

    I found three incorrect explanations of section 9.4.6 User-Controlled Refresh.

    1. Page 223, Note:, "If you enable the auto-precharge control,..."
    should be "If you enable the user controled refresh,...".

    2. Page 223, 9.4.6.1 Back-to-Back User-Controlled Refresh Usage,
    Step 1 to write the cfg_user_rfsh_en register should not be done.
    If we write to the register, we do not receive acknolegement for a long time at step 3.

    3. Page 223, Fighre 87, the tRFC mesurement should start with timing (2) not with (4).

    By my interpretations, my design works fine for back to back user contlloled refresh.

    altera should fix section 9.4.6 User-Controlled Refresh.

    Masaru