Forum Discussion
Occasional ContributorUser controlled burst refresh
I found three incorrect explanations of section 9.4.6 User-Controlled Refresh.
1. Page 223, Note:, "If you enable the auto-precharge control,..."
should be "If you enable the user controled refresh,...".2. Page 223, 9.4.6.1 Back-to-Back User-Controlled Refresh Usage,
Step 1 to write the cfg_user_rfsh_en register should not be done.
If we write to the register, we do not receive acknolegement for a long time at step 3.3. Page 223, Fighre 87, the tRFC mesurement should start with timing (2) not with (4).
By my interpretations, my design works fine for back to back user contlloled refresh.
altera should fix section 9.4.6 User-Controlled Refresh.
Masaru
Regular ContributorHi Masaru,
1. "Should I clear the mmr_refresh_req register before back-to-back next refresh request?"
- No the IP should handle it.
2. "What happens if I disable the auto-precharge control?
In this case, are both IP planned refresh and user controlled refresh happens?"
- You should control the refresh since the IP doesn't issue the refresh if user controlled refresh is enabled.
3. "What is the relationship of them?
Does the IP parameter define initial state of cfg_user_rfsh_en register?
Is the logical AND condition needed for the user controlled refresh?"
- You don't have to care about that. Only use the MMR interface.
4. "Do I need to handle this register?"
- No need.
Regards,
Adzim
Occasional ContributorHi Adzim,
Thank you for your reply.
1. >- No the IP should handle it.
So, the section "9.4.6.1. Back-to-Back User-Controlled Refresh Usage" should be revised
not to clear the mmr_refresh_req register.
2. >- You should control the refresh since the IP doesn't issue the refresh if user controlled refresh is enabled.
No, original statement said, "If you enable the auto-precharge control,".
Is this statement correct?
3. >- You don't have to care about that. Only use the MMR interface.
Do you mean the Enable User Refresh IP parameter doesn't affect at all?
Can I run user control refresh under IP parameter is off?
4. - No need.
Do you mean I don't need to handle cfg_user_rfsh_en register?
I am confused about your answer.
Masaru
- AdzimZM_Altera
Hi Masaru,
When user control refresh is enabled, user has complete control and responsible to provide sufficient refresh to memory.
The statement in EMIF UG mentioned it here: https://docs.altera.com/r/docs/683663/24.1/external-memory-interfaces-cyclone-10-gx-fpga-ip-user-guide/intel-cyclone-10-gx-emif-ip-ddr3-parameters-controller
The IP should enable the user control refresh already.
I don't think you need to enable it from the user logic.
Regards,
Adzim
- MamaSaru
For my point 4, you said:
>I don't think you need to enable it from the user logic.Is "it" referring cfg_user_rfsh_en register?
- AdzimZM_Altera
Hi MamaSaru ,
"Is "it" referring cfg_user_rfsh_en register?"
-Yes
Maybe you also can try to assert read for one clock cycle only instead of assert read until readdatavalid.
Regards,
Adzim
