Forum Discussion
Contributorupdate DDR3 sdram uniphy to Arria 10
It's a totally different IP, so yes, you'd delete and replace. Documentation here:
Training starts here:
https://www.intel.com/content/www/us/en/programmable/support/training/course/omem1121.html
Regular ContributorHi Dsun01,
Do you have any issue when creating the EMIF IP for Arria 10?
Please let me know later.
Thank you Sstrell for providing the info regarding to the Arria 10 EMIF IP.
Thanks & Regards,
Adzim
ContributorHi Adzim
Yes, I am an old FPGA designer, but new to the platform designer. I don't have time to read the user manual of the Platform Designer line by line yet. just hope it is intuitive enough, so I can figure out during the using of it. ( turns out I am not that smart).
In my case, the new device family not support the old IP, in old design approach, the Megacore generate a new core module, I just need to instantiate it in the design( replace the old one). in the new tools I kind of lost after I create a new qsys. It is not clear for me how to replace the old qsys, and make the project linked and compile. I don't think the compiler is so smart that it will make the connection for me. Any way, I am learning how to use the platform designer. I notice that there are lot of example here and there at module level, like PCIe transceiver, EMIF interface to DDR, is there an example/tutorial to show how to link two blocks like PCIe and EMIF together?
Thanks,
David
