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JuanEscobedo's avatar
JuanEscobedo
Icon for New Contributor rankNew Contributor
4 months ago

Unexpected behavior of DDR3 controller on Arria V GZ when using manual refresh

deHello, I am using the DDR3 controller IP on an Arria V GZ FPGA and I am noticing a different behavior when issuing a refresh request using the manual refresh interface. When issuing the refresh a...
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AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 months ago

Hi Juan,


The activation signal is the ACT signal. I think you haven't touch that signal from your controller module.


Why do you sent the refresh on every 1023 clock cycle? is it to match the tRFC?


Regards,

Adzim