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JuanEscobedo's avatar
JuanEscobedo
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4 months ago

Unexpected behavior of DDR3 controller on Arria V GZ when using manual refresh

deHello, I am using the DDR3 controller IP on an Arria V GZ FPGA and I am noticing a different behavior when issuing a refresh request using the manual refresh interface. When issuing the refresh a...
Memory
JuanEscobedo's avatar
JuanEscobedo
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4 months ago

Another example: here is a read, followed by a write, followed by a refresh request:

But some time later, we have the exact same sequence: read, write, refresh req, but on the next read, data valid starts glitching, which throws off the control state machine (that is why we get another refresh request shortly after).

This is the complete view: