Understanding Polyphase Scaler Taps

Hi Niki,

I think the lack of detail in the docs is a recurring theme for the VIP cores and I hear there may be some effort over the next two or three releases to try and improve on this.

With regards the design flow for the VIP cores, as I understand it there are 3 'classes' of core. Most of the cores were written using an internal high level synthesis language called CUSP. I think the language is similar to C / System C and the compiler still ships as part of Quartus and runs as part of the Analysis and Synthesis stage. This is the first class of ip core. I think this tool has been deprecated for a while now and so the CUSP cores are being converted to a new component based HDL (Verilog) approach.

The second class of IP core is those that have already been converted to the HDL component approach - currently only the Scaler II and Deinterlacer II. Over the next few years all of the current cores will be converted to this approach and a 'II' version of each will appear when it is ready. Eventually the old CUSP cores will be deprecated completely, but the 'I' and 'II' versions of each will coe-exist for a while, as with the Scaler I and Scaler II at the moment.

The third and final class of IP core uses HDL (Verilog), but does not use the component based approach. These cores are the CVI, CVO, Packet Reader and Control Sync. The CVI and CVO will probably not be converted to the component based approach, but the frame reader and control sync probably will so there will eventually be a 'II' version of them too. It is my understanding that the packet reader and control sync were written quickly after CUSP was deprecated by before the component based approach was ready to come out of the oven, just to fill some gaps that users were requesting.

The new component based approach is (I think) quite interesting - The VIP cores are composed of smaller cores internally that operate on a line by line basis, rather than frame by frame. Internally the frame packets are broken into smaller packets that are just one line each, allowing components to be shared or time division multiplexed in full system designs. At the moment the base components are hidden, but I think the plan is to eventually offer an 'advanced user' license that will make them visible to users to build systems in Qsys. There is a 4K upscale reference design available (or available soon) that uses these components if you are interested in more info on this.

Hope this helps.

Regards,

Kieron