Two questions about LPDDR3 EMIF controller

Hi KCMurphy,

"1. If the clock skew (phase relationship) is fixed, is it the same from reset to reset and in each device, and if possible, what is it? Normally a PLL has a skew parameter but for this IP that parameter is not visible. Other parts of the design MUST use the reference clock as the output of a PLL (such as the EMIF user-clock) is generally not stable enough."

There are some hidden parameter inside the IP parameter GUI.

You can view the hidden parameter by right-click on IP name and click show hidden parameter.

"2. In simulation, it appears that if the controller is set for CHIP-ROW-BANK-COLUMN, the controller changes the BANK. If set for CHIP-BANK-ROW-COLUMN it changes the ROW. IS this accurate?"

Yes it's accurate. It's control the bank/row switching whether row to bank or bank to row.

It is the address ordering setting where the controller will manage the mapping between Avalon address and memory device address.

Regards,

Adzim