tse ip core communicate with pc

hi, I instantiate the tse ip core with configuration of 10,100/1000Mb mac and RGMII interface in my project to communicate with pc,then initialize the register space of mac with the recommended initialization sequences in ug(except for the initialization of external phy using MDIO).The design works correctly with the simulation of modelsim. When i program my design on Cyclone IV GX EP4CGX150DF FPGA Development Board,the led of RX on the boad blinking and the led of 1000 and DUP are lightening.But i use the signaltap to capture the signals of mac interface,it can be seen that there are no signals on the interface of rx_clk,rx_control and rgmii_in,and the config statemachine can't work correctly as simulation, it keep state of read software reset and can't clear reset bit automatically as the ug said.I am confused how should i do next. I don't know whether it is caused by incorrect constraints on mac ip and rgmii interface or other reason?thankyou! I will attach my sdc content and signaltapii picture below!# ************************************************************ # Create Clock # ************************************************************ create_clock -name {inclk} -period 8.000 [get_ports {inclk}] create_clock -name {rx_clk} -period 8.000 [get_ports {rx_clk}] # ************************************************************ # Create Generated Clock # ************************************************************ derive_pll_clocks set eth_tx_in_clk pll_inst|altpll_component|auto_generated|pll1|clk[0] set eth_tx_out_clk pll_inst|altpll_component|auto_generated|pll1|clk[1]# ************************************************************# Set Input Delay#************************************************************ set_input_delay -clock rx_clk -min 1.5 [get_ports {rgmii_in

[*] rx_control}] -add_delay set_input_delay -clock rx_clk -max 2.5 [get_ports {rgmii_in

[*] rx_control}] -add_delay set_input_delay -clock rx_clk -clock_fall -min 1.5 [get_ports {rgmii_in

[*] rx_control}] -add_delay set_input_delay -clock rx_clk -clock_fall -max 2.5 [get_ports {rgmii_in

[*] rx_control}] -add_delay#************************************************************# Set Output Delay#************************************************************ set_output_delay -clock $eth_tx_out_clk -max 1 [get_ports {rgmii_out

[*] tx_control}] set_output_delay -clock $eth_tx_out_clk -min -1 [get_ports {rgmii_out

[*] tx_control}] -add_delay set_output_delay -clock $eth_tx_out_clk -clock_fall -max 1 [get_ports {rgmii_out

[*] tx_control}] -add_delay set_output_delay -clock $eth_tx_out_clk -clock_fall -min -1 [get_ports {rgmii_out

[*] tx_control}] -add_delay#************************************************************# Set Clock Groups#************************************************************ set_clock_groups -exclusive -group [get_clocks {inclk eth_tx_in_clk eth_tx_out_clk}] set_clock_groups -exclusive -group [get_clocks {rx_clk}]# ************************************************************# Set False Path#************************************************************ set_false_path -from [get_ports {mdio}] set_false_path -to [get_ports {mdc mdio}] set_false_path -setup -rise_from $eth_tx_in_clk -fall_to $eth_tx_out_clk set_false_path -setup -fall_from $eth_tx_in_clk -rise_to $eth_tx_out_clk set_false_path -hold -rise_from $eth_tx_in_clk -fall_to $eth_tx_out_clk set_false_path -hold -fall_from $eth_tx_in_clk -rise_to $eth_tx_out_clk# ************************************************************# Set Multicycle Path#************************************************************ set_multicycle_path -from $eth_tx_in_clk -to $eth_tx_out_clk -setup -start 2# ************************************************************# Set Maximum Delay#************************************************************ set_max_delay -from $eth_tx_out_clk -to [get_ports {tx_clk}] 20# ************************************************************# Set Minimum Delay#************************************************************ set_min_delay -from $eth_tx_out_clk -to [get_ports {tx_clk}] 0