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Altera_Forum
Honored Contributor
10 years agoTSE doesn't have data on RGMII output, functional simulation works fine (Max 10)
Hi everyone, We are using MAX 10 FPGA development kit that supports 10/100/1000 base-T Ethernet using an external Marvell 88E1111 PHY and Altera Triple-Speed Ethernet MegaCore MAC function. ...
Altera_Forum
Honored Contributor
10 years agoHi Kkaibara,
thanks for your input, appreciate that! Yeah, I realised that SignalTap can not monitor DDIO outputs, it took a while! I added PLL output shifted 90deg to run PHY. I was actually finally able to see the packets coming to the PC and monitor them their with WireShark. However, another issue came up - the packets have screwed headers time to time. So I am sending 400 bytes of data + 16 bytes of headers. And headers have same data that Payload has. I tried to monitor mentioned GMII signals in SignalTap but they also could not be gathered - marked as blue in SignalTap and stay always at zero. Are you sure they can be monitored? Any idea about screwed header data?