Forum Discussion
Altera_Forum
Honored Contributor
13 years agoIt could be a problem with the data cache again, although it is rather odd that it would only get the high (or low) 16 bits of every 32-bit word correctly.
I'd suggest to use signaltap to monitor what the SGDMA is doing, on both the TX fifo (as dsl suggests) and the Avalon master mread interface, to check what address the DMA is using and what it is reading there.