Forum Discussion
Altera_Forum
Honored Contributor
13 years agoDoes the Nios CPU have a data cache? If yes, then it is possible that the values you set aren't written to the TSE, but just in the data cache instead. You can try and disable the data cache, use some IOWR/IORD macros to write the TSE registers, use uncached pointers (set bit 31 in the address) or flush the data cache once you are done configuring the TSE, and invalidating it before reading the PHY registers.