TSE + Custom PCB w/Vitesse VSC8601

All,

Great help and suggestions here...this forum is a tremendous resource. I finally got it to work (with a very little bit of egg on my face).

Signal tap was doing its job and not routing the TX DDR signals from the mac to its internals so thats why I could not see them. I rerouted them to an external header and looked at them via an Agilent InfiniiVision scope's digital inputs to see that I indeed did have clean transitions on my digital lines. Hooked the signals back up to the PHY's I/O pins and nothing. Apparently the probing of the vias close the PHY was being impeded by solder mask and it took a very specific angle to get at the TX pins. The signals looked great there afterwards, although I did increase the drive strength to maximum current from the FPGA just for good measure. So it was clearly a timing/config problem. Reviewed the default startup config of the registers (CMODE pins on the Vitesse chip) and found register 23 (0x17) had not been configured properly...the delay wasn't set since some engineer (me) didn't properly configure the CMODE resistors. For the next person I've included my configuration and init code below for the SSS:

// locate this at the top of iniche_init.c

void vitesse_phy_cfg()

{

int x,tmp;

printf("Configuring vitesse VSC8601 phy\n");

printf("REG 0 - Mode Control\n");

tmp = 0x1140;

IOWR(TSE_MAC_BASE,0x80 + 0,tmp); // Enable Full duplex...

printf("REG 17 - Extended phy Control\n");

tmp = 0x1120;

IOWR(TSE_MAC_BASE,0x80 + 0x17,tmp); // this is the important line here...add 2ns of delay and activate actiphy

printf("VSC8601 phy Registers...\n");

for(x=0x80;x < 0x80+29;x++)

{

tmp = IORD(TSE_MAC_BASE,x);

printf("addr: %x, dta: %x\n",x - 0x80,tmp);

}

}

// put this at the top of SSSInitialTask

INT8U error_code;

INT32U x,tmp;

//Print out the regs to see if it comms with any phy's

for(x=0;x<0x320/4;x++)

{

tmp = IORD(TSE_MAC_BASE,x);

printf("addr: 0x%X, dta: 0x%X\n",x,tmp);

}

//Add profile

alt_tse_phy_profile VSC8601 = {"vitesse VSC8601", //

0x1C1, // vitesse OUI

0x02, // Vender Model Number

1, // Model Revision Number

0x1C, // Location of Status Register

3, // Location of Speed Status

5, // Location of duplex Status

0, // Location of Link Status

&vitesse_phy_cfg // Function pointer to configure marvell PHY

&#12288;

};

alt_tse_phy_add_profile(&VSC8601);

&#12288;

alt_tse_system_mac sys_mac = {TSE_SYSTEM_MAC(TSE_MAC)};

alt_tse_system_sgdma sys_sgdma = {TSE_SYSTEM_SGDMA(SGDMA_TX, SGDMA_RX)};

alt_tse_system_desc_mem sys_mem = {TSE_SYSTEM_DESC_MEM(DESCRIPTOR_MEMORY)};

alt_tse_system_shared_fifo sys_sfifo = {TSE_SYSTEM_NO_SHARED_FIFO()};

alt_tse_system_phy sys_phy = {TSE_SYSTEM_PHY(0, NULL)};

alt_tse_system_add_sys(&sys_mac, &sys_sgdma, &sys_mem, &sys_sfifo, &sys_phy );