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FFAA's avatar
FFAA
Icon for New Contributor rankNew Contributor
2 years ago

tripple speed ethernet system side connections the FPGA HPS processor

how do i connect the and handle (the streaming ) the system side to an HPS in an FPGA design.. The current design has the Avalon MM interface connection but not streaming connections. How do the ...
Ethernet
Jeet14's avatar
Jeet14
Icon for Frequent Contributor rankFrequent Contributor
12 months ago

Hi,


We have TSE design with the HPS on the A10 SoC. In this TSE is configured as Avalon memory map interface.

https://www.rocketboards.org/foswiki/Documentation/A10TSEReferenceDesignLTS


For TSE configuration as Avalon streaming interface, you can refer the below link which is with NIOS II/V.

https://www.intel.com/content/www/us/en/design-example/714912/intel-arria-10-fpga-nios-ii-processor-simple-socket-server-design-example.html

https://www.intel.com/content/www/us/en/design-example/763968/arria-10-fpga-simple-socket-server-for-the-nios-v-m-processor-design-example.html


You can take above as reference while working HPS.


Regards

Tiwari