tripple speed ethernet system side connections the FPGA HPS processor

Hi,

Please do allow sometime to check if there is any reference design with Avalon Streaming Interface (HPS+TSE). I will update you soon.

Regards

Tiwari

Hi,

We have TSE design with the HPS on the A10 SoC. In this TSE is configured as Avalon memory map interface.

https://www.rocketboards.org/foswiki/Documentation/A10TSEReferenceDesignLTS

For TSE configuration as Avalon streaming interface, you can refer the below link which is with NIOS II/V.

https://www.intel.com/content/www/us/en/design-example/714912/intel-arria-10-fpga-nios-ii-processor-simple-socket-server-design-example.html

https://www.intel.com/content/www/us/en/design-example/763968/arria-10-fpga-simple-socket-server-for-the-nios-v-m-processor-design-example.html

You can take above as reference while working HPS.

Regards

Tiwari

Hi

Please let me know if there is any query on this.

Regards

Tiwari

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