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DBart1's avatar
DBart1
Icon for New Contributor rankNew Contributor
6 years ago

Triple Speed Ethernet MDIO constraint

I am trying to constrain the MDIO port using set_input_delay for the Altera TSE IP core. I am a bit confused because the PHY chip & IEEE spec show a max 300ns clock to out relative to the MDC clock. ...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

HI,

My point is user doesn't really need to constraint this port in the first place as long as the operating frequency doesn't exceed 2.5MHz.

Thanks.

Regards,

dlim