Forum Discussion

AThom47's avatar
AThom47
Icon for New Contributor rankNew Contributor
6 years ago
Solved

Triple Speed Ethernet IP - 1000BASE-X/SGMII PCS only - word alignment included?

When implementing the Triple Speed Ethernet IP with the core variation "1000BASE-X/SGMII PCS only" WITHOUT built in transceiver (Transceiver type selection is set to "None") does the IP do word align...
  • AThom47's avatar
    AThom47
    6 years ago

    I have tried this in hardware since I asked and the answer from Nathan above is incorrect. The 1000BASE-X/SGMII PCS only version of the tripe speed ethernet IP actually does word alignment internally. Word alignment on the tbi interface out of the rx serdes is NOT needed.

    Also, the tse user guide actually states that in the port description:

    "tbi_rx_d[9:0] - TBI receive data. This bus carries the data from the external SERDES. Synchronize the bus with tbi_rx_clk. The data can be arbitrary aligned."

    Just wanted to update if anyone else is ever wondering about this.

Nathan_R_Intel's avatar
Nathan_R_Intel
Icon for Contributor rankContributor
6 years ago

Hie,

Based on your last response, I re-investigated the Triple Speed Ethernet (TSE) IP in 1000Base-x/SGMIII PCS configuration.

You are correct, currently the incoming TBI receive signal does not require the data to be aligned. My findings is aligned with your investigation.

My apologies, for the previous incorrect description. I configured the TSE IP with 1000Base-X/SGMII PCS only and selected the Transceiver and noticed the hard word aligner block was selected. Hence, I made my conclusion from there that word alignment is only done if transceiver is selected.

Hence, further investigation showed that 8B/10B decoder on the SGMII PCS has additional logic to determine the correct word boundary.

My apologies again for the technical mistake.

Regards,

Nathan