Forum Discussion
New ContributorTriple speed Ethernet & SGMII
Hi,
The extra 0xD5 value looks like a start frame delimiter (SFD) packet that byright TSE MAC should removed. User should see destination address as first packet coming our from TSE RX path to Avalon ST interface.
You can refer to TSE user guide doc (page 195, Figure 82 : MAC Ethernet Frame Format" for detail.
I think you need to slowly trace back the RX path to see where does this extra 0xD5 come from
- Eg : External RX PHY -> TBI -> TSE PCS SGMII -> GMII/MII -> TSE MAC -> Avalon ST bus
- For a start, maybe you can add in MII interface bus (since you are running 100M) into signal_tap to check on the receive data first. Refer to (page 107, figure 46) to check out MAC interface signals list that contains the MII interface bus
- This helps to isolate whether TSE MAC is receiving correct Rx data in the first place or not
You can also generate TSE simulation example design project using your existing TSE IP setting. This will give you extra flexibility to look into TSE IP interface signals to understand the expected behaviour
Thanks.
Regards,
dlim
Regular ContributorHi,
The extra 0xD5 value looks like a start frame delimiter (SFD) packet that byright TSE MAC should removed. User should see destination address as first packet coming our from TSE RX path to Avalon ST interface.
You can refer to TSE user guide doc (page 195, Figure 82 : MAC Ethernet Frame Format" for detail.
I think you need to slowly trace back the RX path to see where does this extra 0xD5 come from
- Eg : External RX PHY -> TBI -> TSE PCS SGMII -> GMII/MII -> TSE MAC -> Avalon ST bus
- For a start, maybe you can add in MII interface bus (since you are running 100M) into signal_tap to check on the receive data first. Refer to (page 107, figure 46) to check out MAC interface signals list that contains the MII interface bus
- This helps to isolate whether TSE MAC is receiving correct Rx data in the first place or not
You can also generate TSE simulation example design project using your existing TSE IP setting. This will give you extra flexibility to look into TSE IP interface signals to understand the expected behaviour
Thanks.
Regards,
dlim
New ContributorSorry for the delay...
Thank you @Deshi_Intel for the reply.
It's (partly) solved...
Ethernet scheme was the following:
RJ45 <-> External PHY <-- TBI --> PCS SGMII <-- GMII/MII --> MAC <-- Avalon --> Own code
RJ45 and external PHY previously operate at 100M while others devices (PCS and MAC) operate at 1G.
It seems that the PHY was not able to perform 100M to 1G translation. When I connect all four pairs of the PHY to the RJ45, it works.
So, it's not totally satisfying (I think that I must configure PHY, PCS and MAC at the same speed and not in autonegotiate mode and I think that I've got a clock problem too) but I can move forward on my own now.
Many thanks!
