Honored Contributor
Honored ContributorWhat you have to do is create or derive PLL clocks yourself and only then put their names to TSE mac SDC like (FF_TX_CLK, FF_RX_CLK) etc. Specifying pins or ports there won't do the job.
After you are done with that you have to make sure you constrain RGMII input and output pins properly (i.e. apply proper pin delays, set false path etc). I am not sure what board you have, though. I have Arria II GX 6G with Marvell PHY 88E1111 and that PHY works with center-aligned I/O. You have to check your reference manual. I recommend you dive deep into AN477 — http://www.altera.com/literature/an/an477.pdf. It describes RGMII timing, has SDC examples etc. Here are also some articles that were a bit useful for me: * http://www.altera.com/support/examples/timequest/exm-tq-ca_ss_in.html * http://www.altera.com/support/examples/timequest/exm-tq-ca_ss_out.html Though if I reckon correctly, those got some typos and are not full. Don't forget to check what your sofware is doing as well. For example, center-aligned I/O can be changed to edge-aligned by enabling RX & TX delays on the PHY through MDIO (for Marvell it is register 20 bits 7 and 1 if I remember correctly). So until you figure out what timing your design expects, you can't really constrain RGMII properly. Also, there must be some examples with dev kit for your board. Check them. P.S.: Oh, boy. I remember the frustration that I had when I was learning how to do that :))) My design was either not sending, not receiving, or both, or dropping packets randomly. Anyhow, it takes some time, a deep though, careful reading of some scattered documentation, and of course experimentation.
