ContributorHi all,
I have a very strange problem on the C10 transceiver.
I am doing a SDI Tx project on 10CX105YF780 and I instantiate a reference design.
After validate the function, I copy all the files to build a new one.
Strange thing is this part new work.
Below is the signal of the GXB and PLL.
Looks like the core is not ready for unknown reason.
Do you have any idea how I could debug this?
Thank you!
BRs,
Bin
Regular ContributorHi,
As I understand it, you observe some problem when using the SDI TX. There is no issue when you are running the reference design. However, when you copy some of the design files and build a new project, the TX seems to be not working.
For your information, as I looked at the signaltap screenshot, it seems like there is no activity at the TX side i.e. no PLL lock. I believe either there is no refclk present to the TX PLL or there are some file missing or incorrect path reference after you copy the files.
Since the default reference design is functioning, I think it would be great for you to start customizing from the reference design instead of copying the files just to avoid any missing or incorrect reference.
Please let me know if there is any concern. Thank you.
ContributorHi CheePin,
Thank you!
For unknown reason, I noticed some of the ref clock pins direction was unknown in Pin planner.
But those pins were already assign as inputs.
Anyway to get this fixed..
Regular ContributorHi,
Thanks for your update. Just to clarify my understanding that your problem has been resolved. Thank you.
ContributorHi CP,
Yes, i followed the instructions.
FYI!
Regular ContributorGlad to hear that your problem is resolved. Thank you.
Regular ContributorHi,
I believe the initial inquiry has been addressed. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
