Honored Contributor
Honored ContributorI think the only way you can do this is if you design your board so that the recovered clock can be routed to an external jitter cleaner, and the reference clock from that jitter cleaner is another REFCLK input. I'm pretty sure I read this idea in the SyncE paper on the SiLabs web
https://www.silabs.com/documents/public/application-notes/an420.pdf I haven't ever had a chance to test that it works though :) The alternative (and more standard way) is to distribute a common REFCLK and then all the links are coherent (phase shifted, but all effectively phase-locked). Why do you need them to be synchronous though? If the payload rate is lower than the data rate, then so long as you have some way of extracting the data (timestamps, headers, etc) you do not need coherent clocks. Cheers, Dave
