Forum Discussion
Occasional ContributorTiming for PLL clock PLL_RECONFIG~FMAX_CAP_FF
Hi Richard,
The design is quite large, so I can't share it. But to the point, the error is within the Reconfigurable PLL IP block. I think it has to do with the strange timing of the "phase_done" signal, which I believe I have accounted for after carefully reading the user guide. I was hoping that you might have some special knowledge from seeing this condition before.
So, that said, I think I'll false path or underconstrain the "clock" to get around the issue and close out this request. Thank you for your help.
Super ContributorHi,
Do you able to share the design with us?
Regards,
Richard Tan
K_CrockerHi Richard,
The design is quite large, so I can't share it. But to the point, the error is within the Reconfigurable PLL IP block. I think it has to do with the strange timing of the "phase_done" signal, which I believe I have accounted for after carefully reading the user guide. I was hoping that you might have some special knowledge from seeing this condition before.
So, that said, I think I'll false path or underconstrain the "clock" to get around the issue and close out this request. Thank you for your help.
