Forum Discussion
SERMASWATHIKA
Contributor
Contributortiming_error_for_pll_afi_clock_on_ddr3_ip_controller
Hi Team, I am checking the design with ddr3 interface, nios processor and other interfaces also in cyclone v gx device(5CGXFC5C6F27C7). I have given memory clock as 400 Mhz(ddr3 ip parameter setti...
TingJiangT_IntelContributor
ContributorHi there, is there any updates on this issue?
SERMASWATHIKAContributor
ContributorHi,
i have checked the design with clk connected from inclk directly and compiled the design.
But still timing violations are there.
i have created another threat for ddr3_timing and sharing project archive with reports.
based on the inputs from that thread, modified the project .
Sharing the project with this
