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SERMASWATHIKA's avatar
SERMASWATHIKA
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2 years ago

timing_error_for_pll_afi_clock_on_ddr3_ip_controller

Hi Team, I am checking the design with ddr3 interface, nios processor and other interfaces also in cyclone v gx device(5CGXFC5C6F27C7). I have given memory clock as 400 Mhz(ddr3 ip parameter setti...
Memory
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Besides, this timing violation on the Platform designer, you also have violation on the DDR itself.

Can you create a separate thread to resolve this timing violation for the DDR part? As this will require tuning the DDR setting in your design. thanks