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SERMASWATHIKA's avatar
SERMASWATHIKA
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2 years ago

timing_error_for_pll_afi_clock_on_ddr3_ip_controller

Hi Team, I am checking the design with ddr3 interface, nios processor and other interfaces also in cyclone v gx device(5CGXFC5C6F27C7). I have given memory clock as 400 Mhz(ddr3 ip parameter setti...
Memory
TingJiangT_Intel's avatar
TingJiangT_Intel
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2 years ago

Hi there, could you please share the ziped design with me, as we need to do some test with it which can't be compiled with only QAR file,


SERMASWATHIKA's avatar
SERMASWATHIKA
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2 years ago

hi ,

i have added the zip file, please check and help me to resolve this issue.