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SERMASWATHIKA
Contributor
Contributortiming_error_for_pll_afi_clock_on_ddr3_ip_controller
Hi Team, I am checking the design with ddr3 interface, nios processor and other interfaces also in cyclone v gx device(5CGXFC5C6F27C7). I have given memory clock as 400 Mhz(ddr3 ip parameter setti...
TingJiangT_IntelContributor
ContributorI see, can you share the modified project with me？
Just choose the same option as the previous one is fine.
- SERMASWATHIKA
Hi,
I have attached the modified project archive. PLease check this and for every compilation timing is varying.
