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SERMASWATHIKA's avatar
SERMASWATHIKA
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2 years ago

timing_error_for_pll_afi_clock_on_ddr3_ip_controller

Hi Team, I am checking the design with ddr3 interface, nios processor and other interfaces also in cyclone v gx device(5CGXFC5C6F27C7). I have given memory clock as 400 Mhz(ddr3 ip parameter setti...
Memory
TingJiangT_Intel's avatar
TingJiangT_Intel
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2 years ago

I see. All the violation path are related to which IP? What about the logic level of these violation paths.


SERMASWATHIKA's avatar
SERMASWATHIKA
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2 years ago

all violations are from ddr3 ip files. all are related to pll_afi_clock signal