Forum Discussion

SERMASWATHIKA's avatar
SERMASWATHIKA
Icon for Contributor rankContributor
2 years ago

timing_error_for_pll_afi_clock_on_ddr3_ip_controller

Hi Team, I am checking the design with ddr3 interface, nios processor and other interfaces also in cyclone v gx device(5CGXFC5C6F27C7). I have given memory clock as 400 Mhz(ddr3 ip parameter setti...
Memory
TingJiangT_Intel's avatar
TingJiangT_Intel
Icon for Contributor rankContributor
2 years ago

Since I can't open your project, please help check following questions:

1, Please check if the launch clock and latch of the violation path are the same clock.

2, Please check the ignored constraint report to make sure all constraints are available.


  • SERMASWATHIKA's avatar
    SERMASWATHIKA
    Icon for Contributor rankContributor
    2 years ago

    Hi,

    I have checked the launch and latch clock, both are same.

    i didnt get the 2nd point you mentioned regarding ignored constraint path.