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SERMASWATHIKA's avatar
SERMASWATHIKA
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2 years ago

timing_error_for_pll_afi_clock_on_ddr3_ip_controller

Hi Team, I am checking the design with ddr3 interface, nios processor and other interfaces also in cyclone v gx device(5CGXFC5C6F27C7). I have given memory clock as 400 Mhz(ddr3 ip parameter setti...
Memory
TingJiangT_Intel's avatar
TingJiangT_Intel
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2 years ago

BTW, you can select the following option when archive the compiled project. With these files we can directly open the timing analyzer, and please check if it can show the paths in timing analyzer after archived.

  • SERMASWATHIKA's avatar
    SERMASWATHIKA
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    2 years ago

    Hi,

    Now i have created the project archive with the options which you have mentioned in the previous message. with version incompatible database file, qar size is exceeded the maximum limit. So i have added qar which has report files alone.