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SERMASWATHIKA's avatar
SERMASWATHIKA
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2 years ago

timing_error_for_pll_afi_clock_on_ddr3_ip_controller

Hi Team, I am checking the design with ddr3 interface, nios processor and other interfaces also in cyclone v gx device(5CGXFC5C6F27C7). I have given memory clock as 400 Mhz(ddr3 ip parameter setti...
Memory
TingJiangT_Intel's avatar
TingJiangT_Intel
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2 years ago

Hi there, I download your project again. now the qsf of the restored project is the same with what you showed. However I still can't start the compilation process with the same issue.

Can the archived project start compilation process from your side?


  • SERMASWATHIKA's avatar
    SERMASWATHIKA
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    2 years ago

    yes, i have compiled the restored archive project , after that only i have shared to you