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SERMASWATHIKA's avatar
SERMASWATHIKA
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2 years ago

timing_error_for_pll_afi_clock_on_ddr3_ip_controller

Hi Team, I am checking the design with ddr3 interface, nios processor and other interfaces also in cyclone v gx device(5CGXFC5C6F27C7). I have given memory clock as 400 Mhz(ddr3 ip parameter setti...
Memory
TingJiangT_Intel's avatar
TingJiangT_Intel
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2 years ago

Hi there, I can't open timing analyzer with the project you provide, please make sure the timing path can be showed in timing analyzer after you archive the project.

Thanks a lot.


  • SERMASWATHIKA's avatar
    SERMASWATHIKA
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    2 years ago

    Hi ,

    I have added the compiled project archive here. i have archived the project in 22.1 . Please compile the project after restoration. then you can open the timing analyser. i have checked in my pc..