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anonimcs's avatar
anonimcs
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2 years ago

Timing constraints of Intel IPs

Hi all, I have a design on Quartus 21.3 Pro and I noticed that the External Memory Interface IP for DDR4 memory has some timing violations within the IP core. I would expect that these kind of IP co...
Memory
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

As we have IP experts for the respective IPs, could you file a new case requesting the EMIF IP owner to review your IP?

They can check if there are any configuration settings that might help with the timing. Typically, the timing within the IP is already managed by the IP's SDC file.


Regards,

Richard Tan



  • anonimcs's avatar
    anonimcs
    Icon for Contributor rankContributor
    2 years ago

    Hi,

    Can't you just forward this forum entry to those experts internally ? I think it would make the most sense for them to see what we've discussed and tried out until this moment.

    Cheers.