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anonimcs's avatar
anonimcs
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2 years ago

Timing constraints of Intel IPs

Hi all, I have a design on Quartus 21.3 Pro and I noticed that the External Memory Interface IP for DDR4 memory has some timing violations within the IP core. I would expect that these kind of IP co...
Memory
RichardT_altera's avatar
RichardT_altera
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2 years ago

I am glad to hear that you are able to close the timing.

With the location assignment being locked out, we are left with optimizing the compiler settings for better placement.


Since the issue has been resolved, can we consider this thread closed?


Regards,

Richard Tan


anonimcs's avatar
anonimcs
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2 years ago

Although the timing is now met, I'm still not satisfied with the way I had to fix the timing violations of the Intel's IP. I would be happy if we can keep the Fitter settings in default (Balanced optimizing) and fix whatever timing violation in the logic itself.